6,380,980: Method and apparatus for recovering video color subcarrier signal
6,377,912: Emulation system with time-multiplexed interconnect
6,377,911: Apparatus for emulation of electronic hardware system
6,373,740: Transmission lines for CMOS integrated circuits
6,366,380: Optical transceiver EMI detuning device
6,366,061: Multiple power supply circuit architecture
6,365,912: Superconducting tunnel junction device
6,365,839: Multi-layer printed circuit board with dual impedance section
6,363,516: Method for hierarchical parasitic extraction of a CMOS design
6,360,191: Method and apparatus for automated design of complex structures using genetic programming
6,359,343: Temperature stabilization in flip chip technology
6,353,906: Testing synchronization circuitry using digital simulation
6,353,433: Digitizer interface
6,351,190: Stage having controlled variable resistance load circuit for use in voltage controlled ring oscillator
RE37,552: System and method for power-efficient charging and discharging of a capacitive load from a single source
6,346,831: Noise tolerant wide-fanin domino circuits
6,345,379: Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist
6,344,758: Interface for low-voltage semiconductor devices
6,342,794: Interface for low-voltage semiconductor devices
6,338,106: I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
6,337,798: Digital circuit decoupling for EMI reduction
6,337,634: Radio frequency data communications device
6,337,590: Digital delay locked loop
6,335,129: Method for repairing pattern defect, photo mask using the method, and semiconductor device manufacturing method employing the photo mask
6,333,940: Integrated digital loop carrier system with virtual tributary mapper circuit
6,333,656: Flip-flops
6,330,666: Multistandard video decoder and decompression system for processing encoded bit streams including start codes and methods relating thereto
6,330,665: Video parser
6,324,679: Register transfer level power optimization with emphasis on glitch analysis and reduction
6,323,859: Method and system for interactively determining and displaying geometric relationship between three dimensional objects based on predetermined geometric constraints and position of an input device
6,323,701: Scheme for reducing leakage current in an input buffer
6,317,125: Saxs video object generation engine
6,317,058: Intelligent traffic control and warning system and method
6,316,975: Radio frequency data communications device
6,314,630: Determinant wing assembly
6,314,553: Circuit synthesis and verification using relative timing
6,314,552: Electronic design creation through architectural exploration
6,314,440: Pseudo random number generator
6,313,703: Use of antiphase signals for predistortion training within an amplifier system
6,310,570: System with adjustable ADC clock phase
6,308,147: Data structure synthesis in hardware using memory transaction translation techniques
6,305,006: Generating candidate architectures for an architectural exploration based electronic design creation process
6,300,819: Circuit including forward body bias from supply voltage and ground nodes
6,298,453: Method of determining signal delay of a resource in a reconfigurable system having multiple resources
6,297,759: Digital-to-analog converter with high-speed output
6,297,668: Serial device compaction for improving integrated circuit layouts
6,297,666: Fully programmable and configurable application specific integrated circuit
6,297,627: Detection of passing magnetic articles with a peak-to-peak percentage threshold detector having a forcing circuit and automatic gain control
6,292,926: Functional module model, pipelined circuit synthesis and pipelined circuit device
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